SH7730 Datasheet, PDF (146/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
Initial
Bit
Bit Name Value R/W Description
31 to 5 
All 0 R
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
4
MMCAW 1
R/W Memory-Mapped Cache Associative Write
0: Memory-mapped cache associative write is disabled.
(A data address error exception will occur.)
1: Memory-mapped cache associative write is enabled.
For further details, refer to section 8.6.5, Memory-
Mapped Cache Associative Write Operation.
3, 2

All 1 R
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
1
BRDSSLP 1
R/W Delay Slot SLEEP Instruction
0: The SLEEP instruction in the delay slot is disabled.
(The SLEEP instruction is taken as a slot illegal
instruction.)
1: The SLEEP instruction in the delay slot is enabled.
0
RTEDS
1
R/W RTE Delay Slot
0: An instruction other than the NOP instruction in the
delay slot of the RTE instruction is disabled. (An
instruction other than the NOP instruction is taken as
a slot illegal instruction).
1: An instruction other than the NOP instruction in the
delay slot of the RTE instruction is enabled.
Note: The initial values of bits 4, 1, and 0 depend on the product. See the manual of the product
for details.
Rev. 1.00 Sep. 19, 2007 Page 98 of 1136
REJ09B0359-0100