SH7730 Datasheet, PDF (1066/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 31 User Debugging Interface (H-UDI)
31.3.3 Interrupt Source Register (SDINT)
SDINT is a 16-bit register that can be read from or written to by the CPU. Specifying an H-UDI
interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While an H-
UDI interrupt command is set in SDIR, SDINT which is connected between the TDI and TDO
pins can be read as a 32-bit register. In this case, the upper 16 bits will be 0 and the lower 16 bits
represent the SDINT value.
Only 0 can be written to the INTREQ bit by the CPU. While this bit is set to 1, an interrupt request
will continue to be generated. This bit, therefore, should be cleared by the interrupt handling
routine. It is initialized by TRST or in the Test-Logic-Reset state.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — — — — — — — INTREQ
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit
Bit Name Initial Value R/W
15 to 1 
All 0
R
0
INTREQ 0
R/W
Description
Reserved
For reading from or writing to these bits, see General
Precautions on Handling of Product.
Interrupt Request
Indicates whether or not an interrupt by an H-UDI
interrupt command has occurred. Clearing this bit to 0
by the CPU cancels an interrupt request. When writing
1 to this bit, the previous value is maintained.
31.3.4 Bypass Register (SDBPR)
SDBPR is a eight-bit register that supports the J-TAG bypass mode. When the BYPASS command
is set to the boundary scan TAP controller, the TDI and TDO are connected by way of SDBPR.
This register cannot be accessed from the CPU regardless of the LSI mode. Though this register is
not initialized by a power-on reset and the TRST pin asserted, initialized to 0 in the Capture-DR
state.
Rev. 1.00 Sep. 19, 2007 Page 1018 of 1136
REJ09B0359-0100