SH7730 Datasheet, PDF (473/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Bit
7 to 2
1, 0
Initial
Bit Name Value R/W
C2MID[5:0] 000000 R/W
C2RID[1:0] 00
R/W
Description
Transfer request module ID5 to ID0 for DMA channel 2
(MID)
See table 12.4.
Transfer request register ID1 and ID0 for DMA channel 2
(RID)
See table 12.4.
• DMARS_2
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
C5MID[5:0]
C5RID[1:0]
C4MID[5:0]
C4RID[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
15 to 10 C5MID[5:0] 000000 R/W
9, 8
C5RID[1:0] 00
R/W
7 to 2 C4MID[5:0] 000000 R/W
1, 0
C4RID[1:0] 00
R/W
Description
Transfer request module ID5 to ID0 for DMA channel 5
(MID)
See table 12.4.
Transfer request register ID1 and ID0 for DMA channel 5
(RID)
See table 12.4.
Transfer request module ID5 to ID0 for DMA channel 4
(MID)
See table 12.4.
Transfer request register ID1 and ID0 for DMA channel 4
(RID)
See table 12.4.
Rev. 1.00 Sep. 19, 2007 Page 425 of 1136
REJ09B0359-0100