SH7730 Datasheet, PDF (485/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
(2) Bus Modes
There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB bits in
CHCR.
(a) Cycle-Steal Mode
In cycle-steal mode, select either normal mode or intermittent mode by the CMS[3:0] bits in
DMAOR.
• Normal mode
In cycle-steal normal mode, the bus mastership is given to another bus master after a one-
transfer-unit (byte, word, longword, 8-byte, 16-byte, or 32-byte unit) DMA transfer. When
another transfer request occurs, the bus mastership is obtained from the other bus master and a
transfer is performed for one transfer unit. When that transfer ends, the bus mastership is
passed to the other bus master. This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination.
Figure 12.6 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
DREQ
Bus mastership returned to CPU once
Bus cycle
CPU
CPU
CPU
DMAC DMAC
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 12.6 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)
• Intermittent mode 16 and intermittent mode 64
In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, 8-byte, 16-byte, or 32-byte unit) is
complete. If the next transfer request occurs after that, the DMAC gets the bus mastership from
other bus master after waiting for 16 or 64 clocks in Bφ count. The DMAC then transfers data
of one unit and returns the bus mastership to other bus master. These operations are repeated
until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus
occupation by DMA transfer than cycle-steal normal mode.
Rev. 1.00 Sep. 19, 2007 Page 437 of 1136
REJ09B0359-0100