SH7730 Datasheet, PDF (772/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Initial
Bit
Bit Name Value R/W Description
5
PE
0
R/W Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data. This setting is only
valid in asynchronous mode. In synchronous mode,
parity bit addition and checking is not performed,
regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked
Note: * When PE is set to 1, an even or odd parity
bit is added to transmit data, depending on
the parity mode (OE) setting. Receive data
parity is checked according to the even/odd
(OE) mode setting.
4
OE
0
R/W Parity Mode
Selects even or odd parity when parity bits are added
and checked. The OE setting is used only when the PE
is set to 1 to enable parity addition and check. The OE
setting is ignored when parity addition and check is
disabled.
0: Even parity*¹
1: Odd parity*²
Notes: 1. If even parity is selected, the parity bit is
added to transmit data to make an even
number of 1s in the transmitted character
and parity bit combined. Receive data is
checked to see if it has an even number of
1s in the received character and parity bit
combined.
2. If odd parity is selected, the parity bit is
added to transmit data to make an odd
number of 1s in the transmitted character
and parity bit combined. Receive data is
checked to see if it has an odd number of
1s in the received character and parity bit
combined.
Rev. 1.00 Sep. 19, 2007 Page 724 of 1136
REJ09B0359-0100