SH7730 Datasheet, PDF (23/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

25.4.1 Overview................................................................................................................ 837
25.4.2 Data Format............................................................................................................ 837
25.4.3 Register Settings..................................................................................................... 839
25.4.4 Clocks .................................................................................................................... 841
25.4.5 Data Transmit/Receive Operation .......................................................................... 842
25.5 Usage Notes ...................................................................................................................... 850
Section 26 A/D Converter..................................................................................857
26.1 Features............................................................................................................................. 857
26.2 Input Pins .......................................................................................................................... 859
26.3 Register Descriptions........................................................................................................ 860
26.3.1 A/D Data Registers A to D (ADDRA to ADDRD)................................................ 861
26.3.2 A/D Control/Status Registers (ADCSR) ................................................................ 862
26.4 Operation .......................................................................................................................... 865
26.4.1 Single Mode ........................................................................................................... 865
26.4.2 Multi Mode ............................................................................................................ 867
26.4.3 Scan Mode.............................................................................................................. 869
26.4.4 Input Sampling and A/D Conversion Time............................................................ 871
26.4.5 External Trigger Input Timing ............................................................................... 872
26.5 Interrupts........................................................................................................................... 873
26.6 Definitions of A/D Conversion Accuracy......................................................................... 873
26.7 Usage Notes ...................................................................................................................... 875
26.7.1 Allowable Signal-Source Impedance ..................................................................... 875
26.7.2 Influence to Absolute Accuracy ............................................................................. 875
26.7.3 Setting Analog Input Voltage................................................................................. 876
26.7.4 Notes on Board Design .......................................................................................... 876
26.7.5 Notes on Countermeasures to Noise ...................................................................... 876
26.7.6 Notes on A/D Conversion ...................................................................................... 877
Section 27 D/A Converter (DAC)......................................................................879
27.1 Features............................................................................................................................. 879
27.2 Input/Output Pins.............................................................................................................. 880
27.3 Register Descriptions........................................................................................................ 880
27.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................... 881
27.3.2 D/A Control Register (DACR)............................................................................... 881
27.4 Operation .......................................................................................................................... 883
Section 28 I/O Port ............................................................................................885
28.1 Register Descriptions........................................................................................................ 885
28.2 Port A................................................................................................................................ 887
Rev. 1.00 Sep. 19, 2007 Page xxiii of xlviii