SH7730 Datasheet, PDF (618/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 19 Compare Match Timer (CMT)
To detect an overflow interrupt, set CMCOR to H'FFFFFFFF. When the values in CMCNT
and CMCOR match, CMCNT is cleared to H'00000000 and the CMF and OVF bits in
CMCSR are set to 1.
Value in
CMCNT
CMCOR
H'00000000
CMF=1
OVF=1 (When an overflow is detected)
Time
Figure 19.3 Counter Operation (Free-Running Operation)
19.4.2 Counter Size
In this module, the size of the counter is selectable as either 16 or 32 bits. This is selected by the
CMS bit in CMCSR.
When the 16-bit size is selected, use a 32-bit value which has H'0000 as its upper half to set
CMCOR.
To detect an overflow interrupt, the value must be set to H'0000FFFF.
19.4.3 Timing for Counting by CMCNT
In this module, the clock signal for each counter can be selected from among the following:
• Peripheral clock (Pφ) scaling for CMCNT_0 to CMCNT_4: 1/8, 1/32, and 1/128
The clock signal for each counter is selected by the CKS[2:0] bits in CMCSR. CMCNT is
incremented on rising edges of the selected clock.
Rev. 1.00 Sep. 19, 2007 Page 570 of 1136
REJ09B0359-0100