SH7730 Datasheet, PDF (811/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Start of transmission
Set transmit trigger number in
TTRG[1:0] in SCAFCR
1
Write transmit data exceeding transmit
trigger number, and clear
2
TDFE flag to 0 after reading 1 from it
Wait
3
1-bit interval elapsed?
No
Yes
Set TE bit in SCASCAR
When using transmit FIFO data 4
interrupt, set TIE bit to 1
1. Set the transmit trigger number
in SCAFCR.
2. Write transmit data to SCAFTDR,
and clear the TDFE flag to 0 after
reading 1 from it.
3. Wait for one bit interval.
4. Transmission is started when the
TE bit in SCASCR is set to 1.
5. After the end of transmission, clear
the TE bit to 0.
TEND =1?
No
Yes
Clear TE bit in SCASCR to 0
5
End of transmission
Figure 23.17 Sample Serial Transmission Flowchart (2)
(Second and Subsequent Transmission)
Rev. 1.00 Sep. 19, 2007 Page 763 of 1136
REJ09B0359-0100