SH7730 Datasheet, PDF (373/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Bit
8
7 to 5
4, 3
2
1, 0
Section 11 Bus State Controller (BSC)
Initial
Bit Name Value R/W Description
BACTV 0
R/W Bank Active Mode
Specifies to access whether in auto-precharge mode
(using READA and WRITA commands) or in bank
active mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT
commands)
Note: Bank active mode can be used only in area 3. In
this case, the bus width can be selected as 16 or
32 bits. When both areas 2 and 3 are set to
SDRAM, specify auto-precharge mode.

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
A3ROW 00
[1:0]
R/W Number of Bits of Row Address for Area 3
Specify the number of bits of the row address for area
3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Setting prohibited

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
A3COL 00
[1:0]
R/W Number of Bits of Column Address for Area 3
Specify the number of bits of the column address for
area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Setting prohibited
Rev. 1.00 Sep. 19, 2007 Page 325 of 1136
REJ09B0359-0100