SH7730 Datasheet, PDF (40/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Figure 33.39 REFOUT, IRQOUT Delay Time ........................................................................ 1098
Figure 33.40 I/O Port Timing ................................................................................................... 1099
Figure 33.41 DREQ Input Timing (DREQ Low Level is Detected) ........................................ 1099
Figure 33.42 TEND, DACK Output Timing ............................................................................ 1100
Figure 33.43 TPU Output Timing ............................................................................................ 1100
Figure 33.44 Oscillation Settling Time when RTC Crystal Oscillator is Turned On ............... 1101
Figure 33.45 I²C Bus Interface Input/Output Timing ............................................................... 1102
Figure 33.46 SIOF_MCK Input Timing ................................................................................... 1103
Figure 33.47 SIOF Transmission/Reception Timing (Master Mode 1, Fall Sampling)............ 1104
Figure 33.48 SIOF Transmission/Reception Timing (Master Mode 1, Rise Sampling)........... 1104
Figure 33.49 SIOF Transmission/Reception Timing (Master Mode 2, Fall Sampling)............ 1105
Figure 33.50 SIOF Transmission/Reception Timing (Master Mode 2, Rise Sampling)........... 1105
Figure 33.51 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) .............. 1106
Figure 33.52 SCK Input Clock Timing .................................................................................... 1107
Figure 33.53 SCI Input/Output Timing in Synchronous Mode ................................................ 1107
Figure 33.54 SIM Module Signal Timing ................................................................................ 1108
Figure 33.55 TCK Input Timing............................................................................................... 1109
Figure 33.56 TRST Input Timing (Reset Hold)........................................................................ 1109
Figure 33.57 H-UDI Data Transfer Timing.............................................................................. 1109
Figure 33.58 MPMD Input Timing .......................................................................................... 1109
Figure 33.59 Output Load Circuit ............................................................................................ 1111
Appendix
Figure B.1 Instruction Prefetch................................................................................................. 1115
Figure D.1 Package Dimensions............................................................................................... 1117
Rev. 1.00 Sep. 19, 2007 Page xl of xlviii