SH7730 Datasheet, PDF (720/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
3
STOP
0
R/W Stop Bit Length
Selects one or two bits as the stop bit length in
asynchronous mode.
When receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
The setting of this bit is only valid in asynchronous
mode. It is ignored in clock synchronous mode because
no stop bits are added.
0: One stop bit*¹
1: Two stop bits*²
2

Notes: 1. When transmitting, a single 1-valued bit is
added at the end of each character for
transmission.
2. When transmitting, two 1-valued bits are
added at the end of each character for
transmission.
0
R Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
CKS[1:0] 00
R/W Clock Select
Select the internal clock source of the on-chip baud rate
generator.
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ: Peripheral clock
Rev. 1.00 Sep. 19, 2007 Page 672 of 1136
REJ09B0359-0100