SH7730 Datasheet, PDF (12/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

7.7.5 UTLB Data Array (TLB Compatible Mode) ............................................................ 201
7.7.6 UTLB Data Array (TLB Extended Mode)................................................................ 202
7.8 Usage Notes ...................................................................................................................... 204
7.8.1 Note on Using LDTLB Instruction ........................................................................... 204
Section 8 Caches................................................................................................ 205
8.1 Features............................................................................................................................. 205
8.2 Register Descriptions........................................................................................................ 210
8.2.1 Cache Control Register (CCR) ................................................................................. 211
8.2.2 Queue Address Control Register 0 (QACR0)........................................................... 213
8.2.3 Queue Address Control Register 1 (QACR1)........................................................... 214
8.2.4 On-Chip Memory Control Register (RAMCR) ........................................................ 215
8.3 Operand Cache Operation................................................................................................. 217
8.3.1 Read Operation ......................................................................................................... 217
8.3.2 Prefetch Operation .................................................................................................... 218
8.3.3 Write Operation ........................................................................................................ 219
8.3.4 Write-Back Buffer .................................................................................................... 220
8.3.5 Write-Through Buffer............................................................................................... 220
8.3.6 OC Two-Way Mode ................................................................................................. 221
8.4 Instruction Cache Operation ............................................................................................. 222
8.4.1 Read Operation ......................................................................................................... 222
8.4.2 Prefetch Operation .................................................................................................... 222
8.4.3 IC Two-Way Mode................................................................................................... 223
8.4.4 Instruction Cache Way Prediction Operation ........................................................... 223
8.5 Cache Operation Instruction ............................................................................................. 224
8.5.1 Coherency between Cache and External Memory .................................................... 224
8.5.2 Prefetch Operation .................................................................................................... 226
8.6 Memory-Mapped Cache Configuration ............................................................................ 227
8.6.1 IC Address Array...................................................................................................... 227
8.6.2 IC Data Array ........................................................................................................... 229
8.6.3 OC Address Array .................................................................................................... 229
8.6.4 OC Data Array.......................................................................................................... 231
8.6.5 Memory-Mapped Cache Associative Write Operation............................................. 232
8.7 Store Queues..................................................................................................................... 233
8.7.1 SQ Configuration...................................................................................................... 233
8.7.2 Writing to SQ............................................................................................................ 233
8.7.3 Transfer to External Memory ................................................................................... 234
8.7.4 Determination of SQ Access Exception ................................................................... 235
8.7.5 Reading from SQ ...................................................................................................... 235
Rev. 1.00 Sep. 19, 2007 Page xii of xlviii