SH7730 Datasheet, PDF (172/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
5.6.3 Interrupts
(1) NMI (Nonmaskable Interrupt)
• Source: NMI pin edge detection
• Transition address: VBR + H'00000600
• Transition operations:
The PC and SR contents for the instruction immediately after this exception is accepted are
saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not
masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the
BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or
accepted. When the INTMU bit in CPUOPM is 1 and the NMI interrupt is accessed, B'1111 is
set to IMASK bit in SR. For details, see section 10, Interrupt Controller (INTC).
NMI()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'0000 01C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
If (cond) SR.IMASK = B'1111;
PC = VBR + H'0000 0600;
}
(2) General Interrupt Request
• Source: The interrupt mask level bits setting in SR is smaller than the interrupt level of
interrupt request, and the BL bit in SR is 0 (accepted at instruction boundary).
• Transition address: VBR + H'00000600
• Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
Rev. 1.00 Sep. 19, 2007 Page 124 of 1136
REJ09B0359-0100