SH7730 Datasheet, PDF (634/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 20 I2C Bus Interface (IIC)
20.3.5 I²C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
Bit: 7
6
5
4
3
2
1
0
TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
TDRE
0
R/W Transmit Data Register Empty
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When the start condition (including retransmission)
is issued
• When slave mode is changed from receive mode to
transmit mode
6
TEND
0
R/W Transmit End
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT
[Setting condition]
• When the ninth clock of SCL rises with the I²C bus
format while the TDRE flag is 1
Rev. 1.00 Sep. 19, 2007 Page 586 of 1136
REJ09B0359-0100