SH7730 Datasheet, PDF (392/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.5.4 CSn Assert Period Expansion
The number of cycles from CSn assertion to RD and WEn assertion can be specified by setting
bits SW[1:0] in CSnWCR. The number of cycles from RD and WEn negation to CSn negation can
be specified by setting bits HW[1:0]. Therefore, a flexible interface to an external device can be
obtained. Figure 11.11 shows an example. A Th cycle and a Tf cycle are added before and after an
ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are
asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices
with slow writing operations.
Th
T1
T2
Tf
Read
CKO
A25 to A0
CSn
RDWR
RD
D31 to D0
RDWR
Write
WEn
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 11.11 CSn Assert Period Expansion
Rev. 1.00 Sep. 19, 2007 Page 344 of 1136
REJ09B0359-0100