SH7730 Datasheet, PDF (534/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 15 RCLK Watchdog Timer (RWDT)
Bit
Bit Name Initial Value R/W Description
5
WRFLG 0
R
Write Status Flag
The writing to the RWTCNT is disabled during this bit
is 1.The writing to the RWTCNT is masked for the
prescribed period to synchronize after the writing to
the RWTCNT. Confirm that this bit is 0 to write to
continuously the RWTCNT.
4
WOVF 0
R/W Indicates that the RWTCNT has overflowed. Write 0
to this bit before using the RWDT.
0: No overflow
1: RWTCNT has overflowed
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0 CKS[2:0] 111
R/W RCLK Clock Select
These bits select the clock to be used for the
RWTCNT count from the eight types obtainable by
dividing the RCLK clock. The overflow period that is
shown inside the parenthesis in the table is the value
when the RCLK clock is 32.768 kHz (EXTAL clock =
33.4 MHz).
000: Rφ (7.9 ms)
001: Rφ /4 (31.5 ms)
010: Rφ /16 (126.0 ms)
011: Rφ /32 (252.0 ms)
100: Rφ /64 (503.0 ms)
101: Rφ /128 (1.0 s)
110: Rφ /1024 (8.1 s)
111: Rφ /4096 (32.2 s)
Notes: * If bits CKS[2:0] are modified when the RWDT is operating, the up-count may not be
performed correctly. Ensure that the bits CKS[2:0] are modified only when the RWDT is
not operating.
Rev. 1.00 Sep. 19, 2007 Page 486 of 1136
REJ09B0359-0100