SH7730 Datasheet, PDF (706/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
(4) 16-bit Stereo Data (1)
L/R method, rising edge sampling, slot No.0 used for left channel data, slot No.1 used for right
channel data, and frame length = 32 bits
1 frame
SIOFSCK
SIOFSYNC
SIOFTXD
SIOFRXD
L-channel data
R-channel data
Slot No.0
No bit delay
Slot No.1
Specifications: TRMD[1:0] = 11,REDG = 1,
FL[3:0] = 1100 (frame length: 32 bits)
TDLE = 1,
TDLA[3:0] = 0000, TDRE = 1, TDRA[3:0] = 0001,
RDLE = 1,
RDLA[3:0] = 0000, RDRE = 1, RDRA[3:0] = 0001,
CD0E = 0,
CD0A[3:0] = 0000, CD1E = 0,
CD1A[3:0] = 0000
Figure 21.16 Transmit and Receive Timing (16-Bit Stereo Data (1))
(5) 16-bit Stereo Data (2)
L/R method, rising edge sampling, slot No.0 used for left-channel transmit data, slot No.1 used for
left-channel receive data, slot No.2 used for right-channel transmit data, slot No.3 used for right-
channel receive data, and frame length = 64 bits
SIOFSCK
SIOFSYNC
SIOFTXD
L-channel data
1 frame
R-channel data
SIOFRXD
Slot No.0
L-channel data
Slot No.1
Slot No.2
R-channel data
Slot No.3
No bit delay
Specifications: _{TRMD[1:0] = 11,} REDG = 1,
FL[3:0] = 1101 (frame length: 64 bits),
TDLE = 1,
TDLA[3:0] = 0000, TDRE = 1,
TDRA[3:0] = 0010,
RDLE = 1,
RDLA[3:0] = 0001, RDRE = 1,
RDRA[3:0] = 0011,
CD0E = 0,
CD0A[3:0] = 0000, CD1E = 0,
CD1A[3:0] = 0000
Figure 21.17 Transmit and Receive Timing (16-Bit Stereo Data (2))
Rev. 1.00 Sep. 19, 2007 Page 658 of 1136
REJ09B0359-0100