SH7730 Datasheet, PDF (472/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
• DMARS0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
C1MID[5:0]
C1RID[1:0]
C0MID[5:0]
C0RID[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
15 to 10 C1MID[5:0] 000000 R/W
9, 8
C1RID[1:0] 00
R/W
7 to 2 C0MID[5:0] 000000 R/W
1, 0
C0RID[1:0] 00
R/W
Description
Transfer request module ID5 to ID0 for DMA channel 1
(MID)
See table 12.4.
Transfer request register ID1 and ID0 for DMA channel 1
(RID)
See table 12.4.
Transfer request module ID5 to ID0 for DMA channel 0
(MID)
See table 12.4
Transfer request register ID1 and ID0 for DMA channel 0
(RID)
See table 12.4.
• DMARS1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
C3MID[5:0]
C3RID[1:0]
C2MID[5:0]
C2RID[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
15 to 10 C3MID[5:0] 000000 R/W
9, 8
C3RID[1:0] 00
R/W
Description
Transfer request module ID5 to ID0 for DMA channel 3
(MID)
See table 12.4.
Transfer request register ID1 and ID0 for DMA channel 3
(RID)
See table 12.4.
Rev. 1.00 Sep. 19, 2007 Page 424 of 1136
REJ09B0359-0100