SH7730 Datasheet, PDF (483/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
(1) Address Modes
(a) Dual Address Mode
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
12.4, data is read to the DMAC from one external memory in a data read cycle, and then that data
is written to the other external memory in a write cycle.
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
First bus cycle
DMAC
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 12.4 Data Flow of Dual Address Mode
Auto request, external request, and on-chip peripheral module request are available for the transfer
request. DACK can be output in read cycle or write cycle in dual address mode. CHCR can
specify whether the DACK is output in read cycle or write cycle.
Rev. 1.00 Sep. 19, 2007 Page 435 of 1136
REJ09B0359-0100