SH7730 Datasheet, PDF (726/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
7
ER
0
R/W* Receive Error
Indicates the occurrence of a framing error or a parity
error during reception.
Clearing the RE bit to 0 in SCSCR does not affect the
ER bit, which retains its value. Even if a receive error
has occurred, the receive data is transferred to
SCFRDR and the receive operation is continued.
Whether or not the data read from SCFRDR includes
any error is shown in the FER and PER bits in
SCFSR.
0: A framing error or parity error has not occurred
during reception.
[Clearing conditions]
• Power-on reset or manual reset
• A 0 is written to ER after 1 is read from it
1: A framing error or parity error has occurred during
reception.
[Setting conditions]
• At the end of reception, the stop bit of the last byte
of receive data is checked and it is found to be 0.
In two stop-bit mode, only the first stop bit is
checked and the second one is not checked.
• The total number of 1s in the receive data plus
parity bit does not match the even/odd parity
specified by the OE bit in SCSMR
Rev. 1.00 Sep. 19, 2007 Page 678 of 1136
REJ09B0359-0100