SH7730 Datasheet, PDF (47/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Table 28.6
Table 28.7
Table 28.8
Table 28.9
Table 28.10
Table 28.11
Table 28.12
Table 28.13
Table 28.14
Table 28.15
Table 28.16
Table 28.17
Table 28.18
Table 28.19
Port D Data Register (PDDR) Read/Write Operations ......................................... 892
Port E Data Register (PEDR) Read/Write Operations .......................................... 895
Port F Data Register (PFDR) Read/Write Operations .......................................... 897
Port G Data Register (PGDR) Read/Write Operations ......................................... 898
Port H Data Register (PHDR) Read/Write Operations ..................................... 900
Port J Data Register (PJDR) Read/Write Operations........................................ 902
Port K Data Register (PKDR) Read/Write Operations ..................................... 904
Port L Data Register (PLDR) Read/Write Operations ...................................... 906
Port M Data Register (PMDR) Read/Write Operations.................................... 907
Port N Data Register (PNDR) Read/Write Operations ..................................... 909
Port Q Data Register (PQDR) Read/Write Operations ..................................... 912
Port R Data Register (PRDR) Read/Write Operations...................................... 914
Port S Data Register (PSDR) Read/Write Operations ...................................... 916
Port T Data Register (PTDR) Read/Write Operations ...................................... 918
Section 29 Pin Function Controller (PFC)
Table 29.1 Multiplexed Pins ................................................................................................... 919
Table 29.2 Register Configuration.......................................................................................... 926
Table 29.3 Register States in Each Operating Mode .............................................................. 927
Section 30 User Break Controller (UBC)
Table 30.1 Register Configuration.......................................................................................... 977
Table 30.2 Register Status in Each Processing State .............................................................. 978
Table 30.3 Settings for Match Data Setting Register.............................................................. 990
Table 30.4 Relation between Operand Sizes and Address Bits to be Compared .................... 998
Section 31 User Debugging Interface (H-UDI)
Table 31.1 Pin Configuration................................................................................................ 1013
Table 31.2 Register Configuration (1) .................................................................................. 1015
Table 31.3 Register Configuration (2) .................................................................................. 1015
Table 31.4 Register States in Each Operating Mode ............................................................ 1016
Table 31.5 Commands Supported by Boundary-Scan TAP Controller ................................ 1019
Section 32 List of Registers
Table 32.1 Register Configuration (1) .................................................................................. 1023
Table 32.1 Register Configuration (2) .................................................................................. 1024
Table 32.1 Register Configuration (3) .................................................................................. 1037
Table 32.2 Register States in Each Operating Mode (1)....................................................... 1038
Table 32.2 Register States in Each Operating Mode (2)....................................................... 1039
Table 32.2 Register States in Each Operating Mode (3)....................................................... 1053
Rev. 1.00 Sep. 19, 2007 Page xlvii of xlviii