SH7730 Datasheet, PDF (1162/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Appendix
Bit
31 to 6
5
4
3
2 to 0
Bit Name

RABD

INTMU

Initial
Value
R/W
H'000000C R
1
R/W
0
R
0
R/W
All 0
R
Description
Reserved
The write value must be the initial value.
Speculative execution bit for subroutine return
0: Instruction fetch for subroutine return is issued
speculatively. When this bit is set to 0, refer to
appendix C, Speculative Execution for Subroutine
Return.
1: Instruction fetch for subroutine return is not issued
speculatively.
Reserved
The write value must be the initial value.
Interrupt mode switch bit
0: SR.IMASK is not changed when an interrupt is
accepted.
1: SR.IMASK is changed to the accepted interrupt level.
Reserved
The write value must be the initial value.
Rev. 1.00 Sep. 19, 2007 Page 1114 of 1136
REJ09B0359-0100