SH7730 Datasheet, PDF (16/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

13.7 Notes on Board Design ..................................................................................................... 463
Section 14 Reset and Power-Down Modes ....................................................... 465
14.1 Features............................................................................................................................. 465
14.1.1 Power-Down Modes .............................................................................................. 465
14.2 Input/Output Pins.............................................................................................................. 466
14.3 Register Descriptions........................................................................................................ 467
14.3.1 Standby Control Register (STBCR)....................................................................... 468
14.3.2 Module Stop Register 0 (MSTPCR0) .................................................................... 469
14.3.3 Module Stop Register 1 (MSTPCR1) .................................................................... 474
14.3.4 Module Stop Register 2 (MSTPCR2) .................................................................... 475
14.4 Operation .......................................................................................................................... 477
14.4.1 Reset....................................................................................................................... 477
14.4.2 Sleep Mode ............................................................................................................ 478
14.4.3 Software Standby Mode......................................................................................... 479
14.4.4 Module Standby Mode........................................................................................... 480
14.4.5 Mode Transitions ................................................................................................... 481
14.4.6 Output Pins Change Timing................................................................................... 481
Section 15 RCLK Watchdog Timer (RWDT)................................................... 483
15.1 Features............................................................................................................................. 483
15.2 Input/Output Pins for RWDT ........................................................................................... 484
15.3 Register Descriptions for RWDT...................................................................................... 484
15.3.1 RCLK Watchdog Timer Counter (RWTCNT)....................................................... 485
15.3.2 RCLK Watchdog Timer Control/Status Register (RWTCSR)............................... 485
15.3.3 Notes on Register Access....................................................................................... 487
15.4 RWDT Usage.................................................................................................................... 488
15.4.1 Control of System Runaway .................................................................................. 488
Section 16 16-Bit Timer Pulse Unit (TPU) ....................................................... 489
16.1 Features............................................................................................................................. 489
16.2 Block Diagram.................................................................................................................. 491
16.3 Input/Output Pin ............................................................................................................... 492
16.4 Register Descriptions........................................................................................................ 493
16.4.1 Timer Control Register (TPUn_TCR).................................................................... 497
16.4.2 Timer Mode Register (TPUn_TMDR)................................................................... 499
16.4.3 Timer I/O Control Register (TPUn_TIOR)............................................................ 501
16.4.4 Timer Interrupt Enable Register (TPUn_TIER)..................................................... 503
16.4.5 Timer Status Registers (TPUn_TSR)..................................................................... 504
16.4.6 Timer Counter (TPUn_TCNT) .............................................................................. 506
Rev. 1.00 Sep. 19, 2007 Page xvi of xlviii