SH7730 Datasheet, PDF (486/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
When the DMAC gets again the bus mastership, DMA transfer can be postponed in case of
entry updating due to cache miss.
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Figure 12.7 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
DREQ
At least 16, 64, or 256 Bφ
(change by the CPU's state of using bus)
Bus cycle
CPU CPU CPU DMAC DMAC CPU
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 12.7 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
(b) Burst Mode
In burst mode, once the DMAC obtains the bus mastership, the transfer is performed continuously
without releasing the bus mastership until the transfer end condition is satisfied. In external
request mode with level detection of the DREQ pin, however, when the DREQ pin is not active,
the bus mastership passes to the other bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Burst mode cannot be used when the on-chip peripheral module is the transfer request source.
Figure 12.8 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read Write Read Write Read Write
Figure 12.8 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
Rev. 1.00 Sep. 19, 2007 Page 438 of 1136
REJ09B0359-0100