SH7730 Datasheet, PDF (367/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
2

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
TRC[1:0] 00
R/W Number of Cycles from REF Command/Self-Refresh
Release to ACTV Command
Specify the number of minimum cycles from issuing the
REF command or releasing self-refresh to issuing the
ACTV command. The setting for areas 2 and 3 is
common.
00: 3 cycles
01: 4 cycles
10: 6 cycles
11: 9 cycles
Note: * If both areas 2 and 3 are specified as SDRAM, TRP1[1:0], TRCD[1:0], TRWL[1:0], and
TRC[1:0] bit settings are common.
If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or byte-selection SRAM.
Rev. 1.00 Sep. 19, 2007 Page 319 of 1136
REJ09B0359-0100