SH7730 Datasheet, PDF(764/1188 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

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SH7730 Datasheet, PDF (764/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

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Section 23 Serial Communication Interface with FIFO A (SCIFA)

â¢ Asynchronous mode:

Serial data communications are performed by start-stop in character units. The SCI can

communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous

communication interface adapter (ACIA), or any other communications chip that employs a

standard asynchronous serial system. There are eight selectable serial data communication

formats.

ï£§ Data length: Seven or eight bits

ï£§ Stop bit length: One or two bits

ï£§ Parity: Even, odd, or none

ï£§ LSB first

ï£§ Receive error detection: Parity, framing, and overrun errors

ï£§ Break detection: Break is detected when the receive data next the generated framing error

is the space 0 level and has the framing error.

â¢ Synchronous mode:

Serial data communication is synchronized with a clock. Serial data communication can be

carried out with other chips that have a synchronous communication function.

ï£§ Data length: 8 bits

ï£§ LSB-first transfer

Rev. 1.00 Sep. 19, 2007 Page 716 of 1136

REJ09B0359-0100

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