SH7730 Datasheet, PDF (116/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
Table 3.12 Floating-Point Control Instructions
Instruction
LDS Rm,FPSCR
LDS Rm,FPUL
LDS.L @Rm+,FPSCR
LDS.L @Rm+,FPUL
STS FPSCR,Rn
STS FPUL,Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Operation
Rm → FPSCR
Rm → FPUL
(Rm) → FPSCR, Rm+4 → Rm
(Rm) → FPUL, Rm+4 → Rm
FPSCR → Rn
FPUL → Rn
Rn – 4 → Rn, FPSCR → (Rn)
Rn – 4 → Rn, FPUL → (Rn)
Instruction Code
0100mmmm01101010
0100mmmm01011010
0100mmmm01100110
0100mmmm01010110
0000nnnn01101010
0000nnnn01011010
0100nnnn01100010
0100nnnn01010010
Privileged T Bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 3.13 Floating-Point Graphics Acceleration Instructions
Instruction
Operation
Instruction Code
Privileged T Bit
FMOV DRm,XDn
DRm → XDn
1111nnn1mmm01100 —
—
FMOV XDm,DRn
XDm → DRn
1111nnn0mmm11100 —
—
FMOV XDm,XDn
XDm → XDn
1111nnn1mmm11100 —
—
FMOV @Rm,XDn
(Rm) → XDn
1111nnn1mmmm1000 —
—
FMOV @Rm+,XDn
(Rm) → XDn, Rm + 8 → Rm
1111nnn1mmmm1001 —
—
FMOV @(R0,Rm),XDn (R0 + Rm) → XDn
1111nnn1mmmm0110 —
—
FMOV XDm,@Rn
XDm → (Rn)
1111nnnnmmm11010 —
—
FMOV XDm,@-Rn
Rn – 8 → Rn, XDm → (Rn)
1111nnnnmmm11011 —
—
FMOV XDm,@(R0,Rn) XDm → (R0 + Rn)
1111nnnnmmm10111 —
—
FIPR FVm,FVn
inner_product (FVm, FVn) →
1111nnmm11101101 —
—
FR[n+3]
FTRV XMTRX,FVn transform_vector (XMTRX, FVn) → 1111nn0111111101 —
—
FVn
FRCHG
~FPSCR.FR → FPSCR.FR
1111101111111101 —
—
FSCHG
~FPSCR.SZ → FPSCR.SZ
1111001111111101 —
—
FPCHG
~FPSCR.PR → FPSCR.PR
1111011111111101 

FSRRA FRn
1/sqrt(FRn) → FRn
1111nnnn01111101 

FSCA FPUL,DRn
sin(FPUL) → FRn
cos(FPUL) → FR[n + 1]
1111nnn011111101 

Note: * sqrt(FRn) is the square root of FRn.
Rev. 1.00 Sep. 19, 2007 Page 68 of 1136
REJ09B0359-0100