SH7730 Datasheet, PDF (1177/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Index
Numerics
16-Bit timer pulse unit (TPU)................. 489
A
A/D converter ......................................... 857
Address space identifier (ASID)............. 155
Address translation ................................. 154
Addressing modes..................................... 51
Area division........................................... 282
Arithmetic operation instructions ............. 59
ASID....................................................... 168
Asynchronous mode ............................... 745
Auto-Reload Count Operation ................ 557
Auto-Request mode ................................ 427
B
Baud rate generator................................. 639
Big endian......................................... 44, 330
Bit synchronous circuit ........................... 607
Branch instructions ................................... 63
Burst mode.............................................. 438
Bus state controller (BSC) ...................... 277
C
Cacheability bit....................................... 169
Caches..................................................... 205
Clock pulse generator (CPG).................. 449
Clocked synchronous mode .................... 703
Compare match timer (CMT) ................. 561
Control registers ....................................... 30
CRC Engine............................................ 809
Cycle-steal mode .................................... 437
D
D/A converter (DAC) ............................. 879
Data address error ................................... 114
Data TLB miss exception................ 108, 190
Data TLB multiple hit exception ............ 190
Data TLB multiple-hit exception ............ 107
Data TLB protection violation
exception......................................... 111, 192
Delay slot .................................................. 49
Delayed branches ...................................... 49
Direct memory access controller
(DMAC).................................................. 403
Dirty bit................................................... 170
Division by zero...................................... 142
Double-precision floating-point
extended registers...................................... 35
Double-precision floating-point
registers..................................................... 35
Dual address mode.................................. 435
E
Effective address....................................... 51
Exception flow ........................................ 102
Exception handling ................................... 93
Exception/interrupt codes ....................... 100
Execution cycles ....................................... 83
External request mode............................. 427
F
Fixed mode ............................................. 431
Fixed-point transfer instructions ............... 57
Floating-point control instructions............ 68
Floating-point double-precision
instructions................................................ 67
Rev. 1.00 Sep. 19, 2007 Page 1129 of 1136
REJ09B0359-0100