SH7730 Datasheet, PDF (122/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 4 Pipelining
(4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I1
I2
I3
ID s1
s2
s3 WB
(4-2) LDC to DBR/SGR: 4 issue cycles
I1
I2
I3
ID s1
s2
s3 WB
ID
ID
ID
(4-3) LDC to GBR: 1 issue cycle
I1
I2
I3
ID s1
s2
s3 WB
(4-4) LDC to SR: 4 issue cycles + 4 branch cycles
I1
I2
I3
ID E1s1 E2s2 E3s3 WB
ID
ID
ID
(4-5) LDC.L to Rp_BANK/SSR/SPC/VBR: 1 issue cycle
(I1) (I2) (I3) (ID)
(Branch to the
next instruction.)
I1
I2
I3
ID S1 S2 S3 WB
(4-6) LDC.L to DBR/SGR: 4 issue cycles
I1
I2
I3
ID S1 S2 S3 WB
ID
ID
ID
(4-7) LDC.L to GBR: 1 issue cycle
I1
I2
I3
ID S1 S2 S3 WB
(4-8) LDC.L to SR: 6 issue cycles + 4 branch cycles
I1
I2
I3
ID E1S1 E2S2 E3S3 WB
ID
ID
ID
ID
ID
(I1) (I2) (I3) (ID)
(Branch to the next instruction.)
Figure 4.2 Instruction Execution Patterns (4)
Rev. 1.00 Sep. 19, 2007 Page 74 of 1136
REJ09B0359-0100