SH7730 Datasheet, PDF (915/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 26 A/D Converter
26.4.2 Multi Mode
Multi mode should be selected when performing A/D conversions on one or more channels. When
the ADST bit in the A/D conversion control/status register (ADCSR) is set to 1 by software, A/D
conversion starts on the first channel (AN0). When two or more channels are selected, after
conversion of the first channel ends, conversion of the second channel (AN1) starts immediately.
When A/D conversions end on the selected channels, the ADST bit is cleared to 0. The conversion
results are transferred for storage into the A/D data registers corresponding to the channels.
When the mode or analog input channel selection must be changed during A/D conversion, to
prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the
necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in
the group. The ADST bit can be set at the same time as the mode or channel selection is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 26.3 shows a timing diagram for this example.
1. Supply of the clock to the ADC is started by setting the MSTPCR2.MSTP227 bit to 1 and
activates AD conversion operation.
2. Multi mode is selected (MULTI = 1), analog input channels AN0 to AN2 are selected (CH1 =
1, CH0 = 0), and A/D conversion is started (ADST = 1).
3. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA.
4. Next, conversion of the second channel (AN1) starts automatically.
5. Conversion proceeds in the same way through the third channel (AN2).
6. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI interrupt is requested at this
time.
7. Supply of the clock to the ADC is halted by setting the MSTPCR2.MSTP227 bit to 0 so that
ADC enters module standby state.
Rev. 1.00 Sep. 19, 2007 Page 867 of 1136
REJ09B0359-0100