SH7730 Datasheet, PDF (200/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
(b) P1 Area
The P1 area does not allow address translation using the TLB but can be accessed using the
cache.
Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address
to 0 gives the corresponding physical address. Whether or not the cache is used is determined
by the CCR setting. When the cache is used, switching between the copy-back method and the
write-through method for write accesses is specified by the CB bit in CCR.
(c) P2 Area
The P2 area does not allow address translation using the TLB and access using the cache.
Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address
to 0 gives the corresponding physical address.
(d) P4 Area
The P4 area is mapped onto the internal resource of this LSI. This area except the store queue
and on-chip memory areas does not allow address translation using the TLB. This area cannot
be accessed using the cache. The P4 area is shown in detail in figure 7.4.
H'E000 0000
H'E400 0000
H'E500 0000
H'E600 0000
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
H'F800 0000
Store queue
Reserved area
On-chip memory area
Reserved area
Instruction cache address array
Instruction cache data array
Instruction TLB address array
Instruction TLB data array
Operand cache address array
Operand cache data array
Unified TLB address array
Unified TLB data array
Reserved area
H'FC00 0000
H'FFFF FFFF
Control register area
Figure 7.4 P4 Area
Rev. 1.00 Sep. 19, 2007 Page 152 of 1136
REJ09B0359-0100