SH7730 Datasheet, PDF (544/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 16 16-Bit Timer Pulse Unit (TPU)
Table 16.4 Register States in Each Operating Mode
Register Abbreviation
Power-On Reset Software Standby Module Standby Sleep
TPU0_TSTR
Initialized
Retained
Retained
Retained
TPU0_TCR0 to TPU0_TCR3
Initialized
Retained
Retained
Retained
TPU0_TMDR0 to TPU0_TMDR3 Initialized
Retained
Retained
Retained
TPU0_TIOR0 to TPU0_TIOR3 Initialized
Retained
Retained
Retained
TPU0_TIER0 to TPU0_TIER3 Initialized
Retained
Retained
Retained
TPU0_TSR0 to TPU0_TSR3
Initialized
Retained
Retained
Retained
TPU0_TCNT0 to TPU0_TCNT3 Initialized
Retained
Retained
Retained
TPU0_TGRnA (n = 0 to 3)
Initialized
Retained
Retained
Retained
TPU0_TGRnB (n = 0 to 3)
Initialized
Retained
Retained
Retained
TPU0_TGRnC (n = 0 to 3)
Initialized
Retained
Retained
Retained
TPU0_TGRnD (n = 0 to 3)
Initialized
Retained
Retained
Retained
TPU1_TSTR
Initialized
Retained
Retained
Retained
TPU1_TCR0, TPU1_TCR1
Initialized
Retained
Retained
Retained
TPU1_TMDR0, TPU1_TMDR1 Initialized
Retained
Retained
Retained
TPU1_TIOR0, TPU1_TIOR1
Initialized
Retained
Retained
Retained
TPU1_TIER0, TPU1_TIER1
Initialized
Retained
Retained
Retained
TPU1_TSR0, TPU1_TSR1
Initialized
Retained
Retained
Retained
TPU1_TCNT0, TPU1_TCNT1 Initialized
Retained
Retained
Retained
TPU1_TGRnA (n = 0, 1)
Initialized
Retained
Retained
Retained
TPU1_TGRnB (n = 0, 1)
Initialized
Retained
Retained
Retained
TPU1_TGRnC (n = 0, 1)
Initialized
Retained
Retained
Retained
TPU1_TGRnD (n = 0, 1)
Initialized
Retained
Retained
Retained
Rev. 1.00 Sep. 19, 2007 Page 496 of 1136
REJ09B0359-0100