SH7730 Datasheet, PDF (815/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Start of simultaneous
transmission/reception
Set receive trigger number in RTRG1
and RTRG0 in SCAFCR, and set ₁
transmit trigger number in TTRG[1:0]
Set TFRST and RFRST bits in
SCAFCR to 1
2
Clear TFRST and RFRST bits in
SCAFCR to 0
Write transmit data to SCAFTDR 3
Read TDFE and RDF bits in SCASSR
TDFE =1?
RDF =1?
No
Yes
Write 0 to TDFE and RDF bits in
SCASSR after reading 1 from them
1. Set the receive trigger number and
transmit trigger number in SCAFCR.
2. Reset the receive FIFO and transmit
FIFO.
3. Write transmit data to SCAFTDR, and
if there is receive data in the FIFO,
read receive data until there is less
than the receive trigger setting number,
read the TDFE and RDF bits in SCASSR,
and if 1, clear to 0.
4. Wait for one bit interval.
5. Transmission/reception is started when
the TE and RE bits in SCASCR are set
to 1. The TE and RE bits must be set
simultaneously.
6. After the end of transmission/reception,
clear the TE and RE bits to 0.
Wait
1-bit interval elapsed?
4
No
Yes
Set TE and RE bits in SCASCR
simultaneously
When using transmit FIFO data
interrupt, set TIE bit to 1
5
When using receive FIFO data
interrupt, set RIE bit to 1
TDFE =1?
RDF =1?
No
Yes
Read receive trigger number of
receive data bytes from SCAFRDR
Clear TE and RE bits in SCASCR to 0 6
End of
transmission/reception
Figure 23.21 Sample Simultaneous Serial Transmission and Reception Flowchart (2)
(Second and Subsequent Transfer)
Rev. 1.00 Sep. 19, 2007 Page 767 of 1136
REJ09B0359-0100