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| SH7730 Datasheet, PDF (503/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series | |||
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Section 13 Clock Pulse Generator (CPG)
Bit
Bit Name
23 to 20 IFC[3:0]
19 to 16 â
15 to 12 SFC[3:0]
11 to 8 BFC[3:0]
7 to 4 â
Initial
Value
Undefined*1
Undefined*1
Undefined*1
Undefined*1
Undefined*1
R/W
R/W
R
R/W
R/W
R
Description
CPU Clock (IÏ) Frequency Division Ratio*2
0000: Ã1/1
1001: Ã1/10
0010: Ã1/2
1010: Ã1/12
0101: Ã1/4
1011: Ã1/16
0111: Ã1/6
1100: Ã1/20
1000: Ã1/8
Other settings are prohibited
Reserved
SH Clock (SÏ) Frequency Division Ratio*2
0000: Ã1/1
1001: Ã1/10
0010: Ã1/2
1010: Ã1/12
0100: Ã1/3
1011: Ã1/16
0101: Ã1/4
1100: Ã1/20
0111: Ã1/6
Other settings are prohibited
1000: Ã1/8
Bus Clock (BÏ) Frequency Division Ratio*2
0000: Ã1/1
1001: Ã1/10
0010: Ã1/2
1010: Ã1/12
0100: Ã1/3
1011: Ã1/16
0101: Ã1/4
1100: Ã1/20
0111: Ã1/6
Other settings are prohibited
1000: Ã1/8
Reserved
Rev. 1.00 Sep. 19, 2007 Page 455 of 1136
REJ09B0359-0100
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