SH7730 Datasheet, PDF (854/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 24 IrDA Interface (IrDA)
(2) Reception of Infrared Light-Receive Pulse Data
The infrared receive (light-receive) pulse data is sent from the infrared transceiver and its
waveform conforming to IrDA standard 1.0 is decoded and transferred to the UART. Figure 24.6
shows the decoding timing.
1.8432-MHz clock
MSFCLK_IN
IRIN
1-bit data
RXD*¹
A low level determined on IRIN
Phase shift can be
controlled in this period
Next IRIN acceptance started*²
Notes:
1. When a low level is detected on the IRIN pin for at least two continuous cycles of the 1.8432-MHz clock
(an internally generated clock), a low pulse having a width of 17 MSFCLK_IN cycles is output.
This eliminates the phase shift (lag) in the IRIN input pulse for one MSFCLK_IN cycle.
2. The next IRIN input can be detected 14 MSFCLK_IN cycles after a low level is determined on the IRIN pin.
Until 14 cycles have passed, a low level on the IRIN pin is not detected as an effective pulse.
This eliminates the phase shift (lead) in the IRIN input pulse for one MSFCLK_IN cycle.
Figure 24.6 Timing for Decoding Infrared Receive (Light-Receive) Pulse Data
Rev. 1.00 Sep. 19, 2007 Page 806 of 1136
REJ09B0359-0100