SH7730 Datasheet, PDF (440/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
(1) Basic Timing for Memory Card Interface
Figure 11.38 shows the basic timing of the PCMCIA IC memory card interface. If areas 5 and 6
in the physical space are specified as the PCMCIA interface, accessing the common memory areas
in areas 5 and 6 automatically accesses the IC memory card interface. If the external bus
frequency (CKO) increases, the setup times and hold times for the address pins (A25 to A0) to RD
and WE, card enable signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) become
insufficient. To prevent this error, the LSI can specify the setup times and hold times for areas 5
and 6 in the physical space independently, using CS5BWCR and CS6BWCR. In the PCMCIA
interface, as in the normal space interface, a software wait or hardware wait can be inserted using
the WAIT pin. Figure 11.39 shows the PCMCIA memory bus wait timing.
Tpcm1
Tpcm1w
Tpcm1w
Tpcm1w
Tpcm2
CKO
A25 to A0
CExx
RDWR
RD
Read
D15 to D0
Write
WE
D15 to D0
BS
Figure 11.38 Basic Access Timing for PCMCIA Memory Card Interface
Rev. 1.00 Sep. 19, 2007 Page 392 of 1136
REJ09B0359-0100