SH7730 Datasheet, PDF (489/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
12.4.4 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extended resource selectors (DMARS) are set, the DMAC transfers
data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit
of data (specified by TS[3:0] setting). In auto request mode, the transfer begins automatically
when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each
transfer. The actual transfer flows vary by address mode and bus mode.
3. When the specified number of transfer have been completed (when DMATCR reaches 0), the
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are
also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0.
Figure 12.10 shows a flowchart of this procedure.
Rev. 1.00 Sep. 19, 2007 Page 441 of 1136
REJ09B0359-0100