SH7730 Datasheet, PDF (801/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
(c) Serial Data Reception
Figures 23.7 and 18.8 show sample serial reception flowcharts. After SCIFA reception is enabled,
use the following procedure to perform serial data reception.
Start reception
Read PER and FER
flags in SCASSR
PER or FER = 1?
(1)
Yes
(1) Receive error handling and break
detection:
Read the DR, ER, and BRK flags in
SCASSR2 to identify any error, perform
the appropriate error handling, then clear
the DR, ER, and BRK flags to 0. In the
case of a framing error, a break can also
be detected by reading the value of the
RXD pin.
No
Error processing
Read RDF flag in SCASSR
(2)
No
RDF = 1?
Yes
Read receive data in SCAFRDR,
and clear RDF flag in
(3)
SCASSR to 0
No
All data received?
(2) SCIFA status check and receive data
read :
Read SCASSR and check that RDF = 1,
then read the receive data in SCAFRDR,
read 1 from the RDF flag, and then clear
the RDF flag to 0.
(3) Serial reception continuation procedure:
To continue serial reception, read at
least the receive trigger set number of
receive data bytes from SCAFRDR, read
1 from the RDF flag, then clear the RDF
flag to 0. The number of receive data
bytes in SCAFRDR can be ascertained
by reading the lower bits of SCAFDR.
Yes
Clear RE bit in SCASCR to 0
End reception
Figure 23.7 Sample Serial Reception Flowchart (1)
Rev. 1.00 Sep. 19, 2007 Page 753 of 1136
REJ09B0359-0100