SH7730 Datasheet, PDF (68/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 1 Overview
Classification Symbol
Function
I/O Description
Operating mode MD0, MD1
control
Clock mode
setting
Input Sets the clock operating mode.
MD3
Area 0 bus
width setting
Input Specifies area 0 bus width (16/32 bits)
MD5
System control RESETP
RESETOUT
Data alignment Input Selects data alignment (big endian or little endian)
setting
Power-on reset Input This LSI enters the power-on reset state when this
request
pin becomes low level.
Power-on reset Output Becomes low level while this LSI is being power-on
output signal
reset.
STATUS0
Processing
state 0
Output Becomes high level in software standby mode.
Interrupt
NMI
controller
(INTC)
Non maskable
interrupt input
pin
Input
Interrupt request signal that is not maskable
IRQ7 to IRQ4, External
IRQ3/IRL3 to interrupt input
IRQ0/IRL0 pins
IRQOUT
Interrupt
request output
pin
Input Inputs of interrupt request signals
Output Signal indicating that an interrupt request has been
generated.
PINTA7 to
PINTA0,
PINTB3 to
PINTB0
Port-interrupt Input Inputs of port interrupt request signals
input pins
Bus Control. A25 to A0 Address bus Input Address bus
D31 to D0
BS
CS0, CS2 to
CS4
Data bus
Bus cycle start
Chip select
Output Data bus
Output Bus cycle start
Output Chip select
CS5A/CE2A
Output Chip select
Active only for address maps 1 and 3
CS5B/CE1A
Corresponds to PCMCIA card select signals D15 to
D8 when the PCMCIA is used.
Output Chip select
Corresponds to PCMCIA card select signals D7 to
D0 when the PCMCIA is used.
Rev. 1.00 Sep. 19, 2007 Page 20 of 1136
REJ09B0359-0100