SH7730 Datasheet, PDF (661/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.1 Mode Register (SIMDR)
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRMD[1:0] SYNCAT REDG
FL[3:0]
TXDIZ RCIM SYNCAC SYNCDL —
—
—
—
Initial value: 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Initial
Bit
Bit Name Value R/W Description
15, 14 TRMD[1:0] 10
R/W Transfer Mode 1, 0
Select transfer mode as shown in table 21.4.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
13
SYNCAT 0
R/W SIOFSYNC Pin Valid Timing
Indicates the position of the SIOFSYNC signal to be
output as a synchronization pulse.
0: At the start-bit data of frame
1: At the last-bit data of slot
12
REDG
0
R/W Receive Data Sampling Edge
0: The SIOFRXD signal is sampled at the falling edge of
SIOFSCK
1: The SIOFRXD signal is sampled at the rising edge of
SIOFSCK
Note: The timing to transmit the SIOFTXD signal is at
the opposite edge of the timing that samples the
SIOFRXD. This bit is valid only in master mode.
Rev. 1.00 Sep. 19, 2007 Page 613 of 1136
REJ09B0359-0100