SH7730 Datasheet, PDF (495/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
CKO
Bus cycle
DREQ
DMAC
CPU
Last DMA transfer
DMAC
CPU
CPU
DACK
TEND
Figure 12.16 DMA Transfer End Signal Timing (Level Detection in Cycle Steal Mode)
When an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external
device is accessed in word units, the DACK and TEND outputs are divided for data alignment.
This example is shown in figure 12.17.
T1 T2 Taw T1 T2
CKO
Address
CS
RD
Data
WEn
DACKn
(Active-low)
TENDn
(Active-low)
WAIT
Note: TEND is asserted for the last transfer unit of the DMA transfer.
When the transfer unit is divided into several bus cycles and CS
is negated between bus cycles, TEND is also divided.
Figure 12.17 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 1.00 Sep. 19, 2007 Page 447 of 1136
REJ09B0359-0100