SH7730 Datasheet, PDF (624/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 20 I2C Bus Interface (IIC)
20.3 Register Descriptions
Table 20.2 shows the register configuration. Table 20.3 shows the register states in each operating
mode.
Table 20.2 Register Configuration
Channel
0
1
Register Name
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus interrupt enable register
I²C bus status register
Slave address register
I²C bus transmit data register
I²C bus receive data register
NF2CYC register
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus interrupt enable register
I²C bus status register
Slave address register
I²C bus transmit data register
I²C bus receive data register
NF2CYC register
Abbreviation
ICCR1_0
ICCR2_0
ICMR_0
ICIER_0
ICSR_0
SAR_0
ICDRT_0
ICDRR_0
NF2CYC_0
ICCR1_1
ICCR2_1
ICMR_1
ICIER_1
ICSR_1
SAR_1
ICDRT_1
ICDRR_1
NF2CYC_1
R/W Address
Access
Size
R/W H'A447 0000 8
R/W H'A447 0001 8
R/W H'A447 0002 8
R/W H'A447 0003 8
R/W H'A447 0004 8
R/W H'A447 0005 8
R/W H'A447 0006 8
R/W H'A447 0007 8
R/W H'A447 0008 8
R/W H'A475 0000 8
R/W H'A475 0001 8
R/W H'A475 0002 8
R/W H'A475 0003 8
R/W H'A475 0004 8
R/W H'A475 0005 8
R/W H'A475 0006 8
R/W H'A475 0007 8
R/W H'A475 0008 8
Rev. 1.00 Sep. 19, 2007 Page 576 of 1136
REJ09B0359-0100