SH7730 Datasheet, PDF (671/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.7 Status Register (SISTR)
SISTR is a 16-bit readable/writable register that shows the SIOF state. Each bit in this register
becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1.
Bit: 15 14 13 12 11 10 9
8
7
— TCRDY TFEMP TDREQ — RCRDY RFFUL RDREQ —
Initial value: 0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R
6
5
4
3
2
1
0
— SAERR FSERR TFOVF TFUDF RFUDF RFOVF
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
TCRDY
0
R
Transmit Control Data Ready
0: Indicates that a write to SITCR is disabled
1: Indicates that a write to SITCR is enabled
• If SITCR is written when this bit is cleared to 0,
SITCR is over-written and the previous contents of
SITCR are not output from the SIOFTXD pin.
• This bit is valid when the TXE bit in SITCR is set to
1.
• This bit indicates a state of the SIOF. If SITCR is
written, the SIOF clears this bit.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
13
TFEMP
0
R
Transmit FIFO Empty
0: Indicates that transmit FIFO is not empty
1: Indicates that transmit FIFO is empty
• This bit is valid when the TXE bit in SICTR is 1.
• This bit indicates a state; if SITDR is written, the
SIOF clears this bit.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Rev. 1.00 Sep. 19, 2007 Page 623 of 1136
REJ09B0359-0100