SH7730 Datasheet, PDF (325/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Section 11 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. The BSC functions enable this LSI
to connect directly with SRAM, SDRAM, and other memory storage devices, and external
devices.
11.1 Features
The BSC has the following features:
1. External address space
• A maximum 32 or 64 Mbytes for each of areas 0, 2, 3, 4, 5A, 5B, 6A, and 6B, which makes a
total of up to 384 Mbytes of external address space (divided into eight areas). (Address map 1)
• A maximum 64 Mbytes for each of areas 0, 2, 3, 4, 5 and 6, which makes a total of up to 384
Mbytes of external address space (divided into six areas). (Address map 2)
• Areas 2 and 3 are merged to form a maximum of 128 Mbytes of area. (Address map 3)
• Each area can be specified as normal space or space of any memory type among byte-selection
SRAM, burst ROM (asynchronous), SDRAM, and PCMCIA.
• Data bus width (8, 16, or 32 bits) is selectable for each area.
For area 0, data bus width is either 16 or 32 bits.
• Controls insertion of wait cycles for each area.
• Controls insertion of wait cycles for each read access and write access.
• Idle cycles in continuous access can be set independently for five cases: read-write (in same
space/different space), read-read (in same space/different space), and the first cycle is a write
access.
2. Normal space interface
• Supports the interface that can directly connect to SRAM.
3. Burst ROM (clock asynchronous) interface
• High-speed access to the ROM that has the page mode function.
Rev. 1.00 Sep. 19, 2007 Page 277 of 1136
REJ09B0359-0100