SH7730 Datasheet, PDF (287/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 9 On-Chip Memory
Initial
Bit
Bit Name Value
9
RMD
0
8
RP
0
7
IC2W
0
6
OC2W
0
5
ICWPD
0
4 to 0 —
All 0
R/W Description
R/W On-Chip Memory Access Mode
Specifies the right of access to the on-chip memory
from the virtual address space.
0: An access in privileged mode is allowed.
(An address error exception occurs in user mode.)
1: An access in user/ privileged mode is allowed.
R/W On-Chip Memory Protection Enable
Selects whether or not to use the protective functions
using ITLB and UTLB for accessing the on-chip
memory from the virtual address space.
0: Protective functions are not used.
1: Protective functions are used.
For further details, refer to section 9.4, On-Chip
Memory Protective Functions.
R/W IC Two-Way Mode
For further details, refer to section 8.4.3, IC Two-Way
Mode.
R/W OC Two-Way Mode
For further details, refer to section 8.3.6, OC Two-Way
Mode.
R/W IC Way Prediction Disable
For further details, refer to section 8.4.4, Instruction
Cache Way Prediction Operation.
R
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
Rev. 1.00 Sep. 19, 2007 Page 239 of 1136
REJ09B0359-0100