SH7730 Datasheet, PDF (390/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.5.3 Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 11.9.
CKO
T1
Tw
T2
A25 to A0
CSn
Read
RDWR
RD
D31 to D0
RDWR
Write
WEn
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 11.9 Wait Timing for Normal Space Access (Software Wait Only)
Rev. 1.00 Sep. 19, 2007 Page 342 of 1136
REJ09B0359-0100