SH7730 Datasheet, PDF (411/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
(4) Single Read
A read access ends in one cycle when data exists in non-cacheable region and the data bus width is
larger than or equal to access size. As the burst length is set to 1 in SDRAM burst read/single
write mode, only the required data is output. Consequently, no unnecessary bus cycles are
generated even when a cache-through area is accessed.
Figure 11.16 shows the single read basic timing.
CKO
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1
Td1
Tde
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 11.16 Basic Timing for Single Read (Auto-Precharge)
(5) Burst Write
A burst write occurs in the following cases in this LSI.
1. Access size in writing is larger than data bus width.
2. Copyback of the cache
3. 16-byte transfer in DMAC (access to non-cacheable region)
Rev. 1.00 Sep. 19, 2007 Page 363 of 1136
REJ09B0359-0100