SH7730 Datasheet, PDF (791/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Initial
Bit
Bit Name
Value R/W Description
0
LOOP
0
R/W Loop Back Test
Internally connects the transmit output pin (TXD) and
receive input pin (RXD) and enables the loop back test.
0: Disables the loop back test
1: Enables the loop back test
23.3.11 FIFO Data Count Register (SCAFDR)
SCAFDR is a 16-bit register which indicates the number of data bytes stored in SCAFRDR. The
SCAFDR is always read from the CPU.
The bits 14 to 8 of this register indicate the number of transmit data bytes stored in SCAFTDR
that have not yet been transmitted.
The bits 6 to 0 of this register indicate the number of receive data bytes stored in SCAFRDR.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
T[6:0]
—
R[6:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
15
—
14 to 8 T[6:0]
7
—
6 to 0 R[6:0]
Initial
Value R/W
0
R
H'00 R
0
R
H'00 R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits indicate the number of non-transmitted data
stored in SCAFTDR. The H'00 means no transmit data,
and the H'40 means that SCAFTDR is full of transmit
data.
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits indicate the number of receive data bytes
stored in SCAFRDR. The H'00 means no receive data,
and the H'40 means that SCAFRDR is full of receive
data.
Rev. 1.00 Sep. 19, 2007 Page 743 of 1136
REJ09B0359-0100