SH7730 Datasheet, PDF (484/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Figure 12.5 shows an example of DMA transfer timing in dual address mode.
CKO
A
Transfer source
address
Transfer destination
address
CSn
D
RD
WEn
DACKn
(Active-low)
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 12.5 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)
Rev. 1.00 Sep. 19, 2007 Page 436 of 1136
REJ09B0359-0100