SH7730 Datasheet, PDF (509/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
13.5 Changing Frequency
The clock controlled by the frequency control register can be changed either by changing the
multiplication ratio of the PLL circuit or by changing the division ratio of the divider. All of these
are controlled by software through the frequency control register. The methods are described
below.
13.5.1 Changing Multiplication Ratio of PLL Circuit
Changing the multiplication ratio of the PLL circuit can be done by simply rewriting the STC[4:0]
bits in FRQCR because the PLL oscillation settling time is internally detected automatically. The
RWDT setting is not required.
13.5.2 Changing Division Ratio
Changing the division ratio can be done by rewriting each set of bits for setting the division ratio
in FRQCR.
13.5.3 Changing Clock Operating Mode
The values of the mode control pins (MD1 and MD0) that define the clock operating mode are
reflected at a power-on reset. Do not change the MD1 and MD0 pin settings during operation.
13.5.4 Turning On/Off of PLL Circuit
The PLL circuit can be turned on or off by rewriting the PLL1E bit in PLLCR.
Similar to when changing the multiplication ratio of the PLL circuit, the oscillation settling time of
the PLL circuit is internally detected automatically.
Rev. 1.00 Sep. 19, 2007 Page 461 of 1136
REJ09B0359-0100